PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 125

• Manufacturer Part Number: PIC17C752
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 15-5: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER1 (ADDRESS 11h, BANK 6)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I
Unused in this mode
0000 = SPI master mode, clock = F
0001 = SPI master mode, clock = F
0010 = SPI master mode, clock = F
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I
0111 = I
1000 = I
1xx1 = Reserved
1x1x = Reserved
SSPOV
R/W-0
2
2
2
2
transmission to be started
(must be cleared in software)
flow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is
not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
care" in transmit mode. SSPOV must be cleared in software in either mode.
C master mode
C mode
C mode
C slave mode
2
2
2
C slave mode, 7-bit address
C slave mode, 10-bit address
C master mode, clock = F
SSPEN
R/W-0
R/W-0
CKP
SSPM3
R/W-0
OSC
OSC
OSC
OSC
Preliminary
/4
/16
/64
/ (4 * (SSPADD+1) )
SSPM2
R/W-0
SSPM1
R/W-0
2
C conditions were not valid for a
SSPM0
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
read as ‘0’
DS30264A-page 125