MPC106ARX66CE MOTOROLA [Motorola, Inc], MPC106ARX66CE Datasheet
MPC106ARX66CE
Related parts for MPC106ARX66CE
MPC106ARX66CE Summary of contents
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Semiconductor Products Sector Technical Data MPC106 PCI Bridge/Memory Controller Hardware Specifications The Motorola MPC106 PCI bridge/memory controller provides a PowerPC™ microprocessor common hardware reference platform (CHRP™) compliant bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect (PCI) bus. ...
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In this document, the term ‘60x’ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601™, PowerPC 603™, or PowerPC 604™ microprocessors. Note that this does not include ...
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The 106 provides a PowerPC microprocessor CHRP-compliant bridge between the PowerPC microprocessor family and the PCI bus. CHRP documentation provides a set of specifications that define a unified personal computer architecture. PCI support allows the rapid design of systems using ...
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Secondary (L2) cache control — Configurable for write-through or write-back operation — Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte — Gbytes of cacheable space — Direct-mapped — Supports byte parity — Supports ...
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General Parameters The following list provides a summary of the general parameters of the 106: Technology Die size Transistor count Logic design Packages Power supply Maximum input rating 1.4 Electrical and Thermal Characteristics This section provides both the AC ...
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Table 2. Recommended Operating Conditions Characteristic Symbol Supply voltage Vdd PLL supply voltage AVdd Input voltage V in Die junction temperature T j Table 3 provides the package thermal characteristics for the 106. Table 3. Package Thermal Characteristics Characteristic CBGA ...
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Mode Full-On Typical Maximum Doze Typical Maximum Nap Typical Maximum Sleep Typical Maximum Suspend Typical Maximum Notes: • Power consumption for common system configurations assuming 50 pF loads • Suspend power-saving mode assumes SYSCLK off and PLL in bypass mode. ...
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Table 6. Clock AC Timing Specifications Num Characteristic — 60x processor bus (core) frequency — VCO frequency — SYSCLK frequency 1 SYSCLK cycle time 2, 3 SYSCLK rise and fall time 4 SYSCLK duty cycle measured at 1.4 V — ...
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Table 7. Input AC Timing Specifications Num Characteristic 10a Group I input signals valid to 60x Bus Clock (input setup) 10a Group II input signals valid to 60x Bus Clock (input setup) 10a Group III input signals valid to 60x ...
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Bus Clock Group I, II, III, and IV INPUTS SYSCLK Group V and VI INPUTS Figure 4 provides the mode select input timing diagram for the 106. HRST 10c MODE PINS Figure 4. Mode Select Input Timing Diagram 1.4.2.3 ...
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Table 8. Output AC Timing Specifications Num Characteristic 12 SYSCLK to output driven (output enable time) 13a SYSCLK to output valid for TS and ARTRY 13b SYSCLK to output valid for all non-PCI signals except TS, ARTRY, RAS[0–7], CAS[0–7], and ...
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Figure 5 provides the output timing diagram for the 106. VM 60x Bus Clock 13b 14 12 ALL Non-PCI OUTPUTS (Except TS and ARTRY) 13a TS ARTRY VM SYSCLK 14 12 ALL PCI OUTPUTS 1.4.3 JTAG AC Timing Specifications Table ...
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Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) Num Characteristic 6 Boundary-scan input data setup time 7 Boundary-scan input data hold time 8 TCK to output data valid 9 TCK to output high impedance 10 TMS, TDI data ...
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Figure 8 provides the boundary-scan timing diagram. TCK Data Inputs Data Outputs Data Outputs Data Outputs Figure 8. Boundary-Scan Timing Diagram Figure 9 provides the test access port timing diagram. TCK TDI, TMS TDO TDO TDO Figure 9. Test Access ...
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Pin Assignments Figure 10 contains the pin assignments for the MPC106, and Figure 11 provides a key to the shading DL26 DL28 DL30 DH31 DH29 V DL24 DL27 DL29 DL31 DH30 MA1/ U ...
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Pinout Listings Table 10 provides the pinout listing for the MPC106. more than once. Signal Name 60x Processor Interface Signals A[0–31] R2, P2, N2, M2, L2, K2, J5, K4, K5, K6, J2, J6, J3, J4, H3, H4, H2, G2, ...
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Signal Name LBCLAIM N4 MCP J11 TA N1 TBST L4 TEA TSIZ[0–2] G3, G4, F3 TT[0–4] G1, H1, K1, L1 XATS P1 (SDMA1) L2 Cache Interface Signals ADS/DALE/BRL2 R3 BA0 T5 (BR3) BA1/BAA/BGL2 P4 ...
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Signal Name CAS/DQM[0–7] J15, H15, G16, E16, G14, G13, F14, E14 CKE/DBGLB J10 FOE D13 MA0/SDBA1/SDMA0/AR0 N15 SDMA1 P1 (XATS) MA1/SDBA0/AR9 U16 MA[2–12]/SDMA[2–12]/AR T16, R16, P15, P16, N16, M15, M16, L15, K15, K16, J16 [10–20] MDLE/SDCAS E13 PAR[0–7]/AR[1–8] D16, D15, ...
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Signal Name SERR E9 STOP A9 TRDY B9 Interrupt, Clock, and Power Management Signals CKO L11 (DWE2) HRST L16 NMI E15 QACK L14 QREQ H16 SYSCLK L6 SUSPEND H14 Test/Configuration Signals PLL[0–3] U11, T11, U12, T12 TCK F13 TDI B13 ...
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Package Description The following sections provide the package parameters and the mechanical dimensions for the 106. 1.7.1 Package Parameters The package parameters are as provided in the following list. The package type mm, ...
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Mechanical Dimensions Figure 12 shows the mechanical dimensions for the MPC106. Top View – F – 0.200 1112 Bottom View ...
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System Design Information This section provides electrical and thermal design recommendations for successful application of the 106. 1.8.1 PLL Configuration The 106 requires a single system clock input, SYSCLK. The SYSCLK frequency dictates the frequency of operation for the ...
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PLL Power Supply Filtering The AVdd power signal is provided on the 106 to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be ...
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MPC106 or by other receivers in the system recommended that these signals be pulled up or restored in some manner by the system. The 60x data ...
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Chip with C4 Encapsulant Ceramic Substrate Printed-Circuit Board Figure 14. Exploded Cross-Sectional View 1.8.5.1 Internal Package Conduction Resistance For this C4/CBGA packaging technology, the intrinsic conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance • The ...
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Board and System-Level Modeling A common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies is the junction-to-ambient thermal resistance. The final chip-junction operating temperature is not only a function of the component-level thermal resistance, but ...
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Document Revision History Table 15 lists significant changes between revisions of this document. Document Revision Rev 0 Initial release Rev 1 Changed VCO maximum frequency in Table 6 to 200 MHz Changed input and Hi-Z leakage current in Table ...
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Ordering Information Figure 16 provides the Motorola part-numbering nomenclature for the 106. In addition to the core frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancements in the ...