MPC106ARX66CE MOTOROLA [Motorola, Inc], MPC106ARX66CE Datasheet - Page 12
MPC106ARX66CE
Manufacturer Part Number
MPC106ARX66CE
Description
PCI Bridge/Memory Controller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MPC106ARX66CE.pdf
(28 pages)
Figure 5 provides the output timing diagram for the 106.
1.4.3 JTAG AC Timing Specifications
Table 9 provides the JTAG AC timing specifications. Assume Vdd = AVdd = 3.3 ± 5% V DC, GND = 0 V
DC, CL = 50 pF, and 0 T
12
(Except TS and
PCI OUTPUTS
60x Bus Clock
Num
ALL Non-PCI
—
1
2
3
4
5
OUTPUTS
SYSCLK
ARTRY)
ARTRY
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4 V
TCK rise and fall times
TRST setup time to TCK rising edge
TRST assert time
ALL
TS
Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)
MPC106 PCI Bridge/Memory Controller Hardware Specifications
12
12
VM
VM
j
14
13b
Characteristic
14
13a
105 °C.
Figure 5. Output Timing Diagram
VM = Midpoint Voltage (1.4V)
15b
15a
16
VM
VM
18
13
19
Min
40
20
10
10
0
0
15a
16
21
Max
25
—
—
—
—
VM
3
MHz
Unit
ns
ns
ns
ns
ns
Notes
—
—
—
1
1
2