MPC106ARX66CE MOTOROLA [Motorola, Inc], MPC106ARX66CE Datasheet - Page 8

• Manufacturer Part Number: MPC106ARX66CE
• Description: PCI Bridge/Memory Controller
• Manufacturer: MOTOROLA [Motorola, Inc]

Figure 2 provides the SYSCLK input timing diagram.
1.4.2.2 Input AC Specifications
Table 7 provides the input AC timing specifications for the 106 as defined in Figure 3 and Figure 4. These
specifications are for operation between 16.67 and 33.33 MHz PCI bus clock (SYSCLK) frequencies.
Assume Vdd = AVdd = 3.3 ± 5% V DC, GND = 0 V DC, and 0 T
8
Notes :
1
2
3
4
5
6
Num
2, 3
Caution : The SYSCLK frequency and PLL[0–3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL[0–3] signal description in Section 1.8, “System Design Information,” for
valid PLL[0–3] settings, and to Section 1.9, “Document Revision History,” for available frequencies and part
numbers.
VCO operating range for extended temperature devices is different. Refer to MPC106ARXTGPNS/D for more
information.
Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
Timing is guaranteed by design and characterization and is not tested.
The total input jitter (short-term and long-term combined) must be under ±200 ps.
PLL-relock time is the maximum time required for PLL lock after a stable Vdd, AVdd, and SYSCLK are reached
during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during the sleep and suspend power-saving modes. Also note that HRST must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time (100 s) during the power-on reset sequence.
—
—
—
—
—
1
4
60x processor bus (core) frequency
VCO frequency
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle measured at 1.4 V
SYSCLK jitter
106 internal PLL relock time
SYSCLK
MPC106 PCI Bridge/Memory Controller Hardware Specifications
Characteristic
VM
Table 6. Clock AC Timing Specifications
Figure 2. SYSCLK Input Timing Diagram
4
1
VM
VM = Midpoint Voltage (1.4 V)
4
16.67
16.67
30.0
Min
120
SYSCLK/Core
40
—
—
—
33/66 MHz
VM
CV
33.33
±200
Max
60.0
200
100
2.0
66
60
IL
CV
j
IH
16.67
16.67
2
105 °C.
30.0
Min
120
SYSCLK/Core
40
—
—
—
33/83.3 MHz
33.33
±200
Max
83.3
60.0
200
100
2.0
60
MHz
MHz
MHz
Unit
ns
ns
ps
%
s
3
Notes
1, 2
4, 6
—
1
1
3
4
5