MPC106ARX66CE MOTOROLA [Motorola, Inc], MPC106ARX66CE Datasheet - Page 13

• Manufacturer Part Number: MPC106ARX66CE
• Description: PCI Bridge/Memory Controller
• Manufacturer: MOTOROLA [Motorola, Inc]

Figure 6 provides the JTAG clock input timing diagram.
Figure 7 provides the TRST timing diagram.
Notes:
1
2
3
4
Num
These values are guaranteed by design, and are not tested
TRST is an asynchronous signal. The setup time is for test purposes only.
Non-test signal input timing with respect to TCK.
Non-test signal output timing with respect to TCK.
10
11
12
13
6
7
8
9
Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
TCK to TDO high impedance
TRST
TCK
TCK
MPC106 PCI Bridge/Memory Controller Hardware Specifications
3
Characteristic
Figure 6. JTAG Clock Input Timing Diagram
Figure 7. TRST Timing Diagram
VM = Midpoint Voltage (1.4 V)
3
5
VM
2
4
Min
15
15
5
0
0
5
0
0
Electrical and Thermal Characteristics
1
VM
Max
—
—
30
30
—
—
15
15
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
VM
Notes
—
—
—
4
3
3
4
1
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