MPC106ARX66CE MOTOROLA [Motorola, Inc], MPC106ARX66CE Datasheet - Page 11

• Manufacturer Part Number: MPC106ARX66CE
• Description: PCI Bridge/Memory Controller
• Manufacturer: MOTOROLA [Motorola, Inc]

1
2
3
4
5
6
7
8
9
Num
Notes:
13a SYSCLK to output valid for TS and
13b SYSCLK to output valid for all non-PCI
14a SYSCLK to output valid (for RAS[0–7]
14b SYSCLK to output valid for PCI signals
15a SYSCLK to output invalid for all
15b SYSCLK to output invalid for PCI
12
18
19
21
These values are guaranteed by design and are not tested.
Output specifications are measured from 1.4 V on the rising edge of the appropriate clock to the TTL level (0.8
V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 5).
The maximum timing specification assumes C L = 50 pF.
The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master
driving them.
When the 106 is configured for asynchronous L2 cache SRAMs, the DWE[0–2] signals have a maximum
SYSCLK to output valid time of (0.5 x t
PCI 3.3 V signaling environment signals are measured from 1.65 V (Vdd ÷ 2) on the rising edge of SYSCLK to
V
The minimum timing specification assumes C L = 0 pF.
t
numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in
nanoseconds) of the parameter in question.
PCI devices which require more than the PCI-specified hold time of T
approaches the PCI-specified allowance of 2ns may not work with the MPC106. For workarounds, see Motorola
application note Designing PCI 2.1-Compliant MPC106 Systems (order number AN1727/D).
sysclk
OH
SYSCLK to output driven (output
enable time)
ARTRY
signals except TS, ARTRY, RAS[0–7],
CAS[0–7], and DWE[0-2]
and CAS[0–7])
non-PCI signals (output hold)
signals (output hold)
SYSCLK to ARTRY high impedance
before precharge (output hold)
SYSCLK to ARTRY precharge enable
SYSCLK to ARTRY high impedance
after precharge
= 3.0 V or V
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as t
OL
Characteristic
MPC106 PCI Bridge/Memory Controller Hardware Specifications
= 0.3 V.
Table 8. Output AC Timing Specifications
PROC
) + 8.0 ns (where t
t
sysclk
(0.4 *
Min
2.0
1.0
1.0
—
—
—
—
—
—
) + 2.0
66 MHz
t
sysclk
PROC
(1.5 *
Max
11.0
7.0
7.0
7.0
8.0
—
—
—
—
) + 8.0
Electrical and Thermal Characteristics
is the 60x bus clock cycle time).
h
= 0ns or systems where clock skew
t
sysclk
(0.4 x
Min
2.0
1.0
1.0
—
—
—
—
—
—
) + 2.0
83.3 MHz
t
sysclk
(1.5 x
Max
11.0
6.0
6.0
6.0
8.0
—
—
—
—
) + 8.0
sysclk
Notes
2, 3, 4
2, 3, 5
7, 10
2, 3
3, 6
8, 1
8, 1
1
7
1
the
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