CY8C34_1105 CYPRESS [Cypress Semiconductor], CY8C34_1105 Datasheet - Page 46

• Manufacturer Part Number: CY8C34_1105
• Description: Programmable System-on-Chip (PSoC) DC to 50 MHz operation
• Manufacturer: CYPRESS [Cypress Semiconductor]

Figure 7-12. Function Mapping Example in a Bank of UDBs
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-13
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
Signals in this category include:
Document Number: 001-53304 Rev. *L
8-Bit
Timer
I2C Slave
UART
Interrupt requests from all digital peripherals in the system.
DMA requests from all digital peripherals in the system.
Digital peripheral data signals that need flexible routing to I/Os.
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
Connection to I/O pins.
Connection to analog system digital signals.
UDB
UDB
UDB
UDB
Quadrature Decoder
illustrates the concept of the digital system
HV
HV
A
B
8-Bit SPI
UDB
UDB
UDB
UDB
HV
HV
B
A
Logic
12-Bit PWM
12-Bit SPI
UDB
UDB
UDB
UDB
16-Bit
PWM
HV
HV
A
B
16-Bit PYRS
8-Bit
Timer
UDB
UDB
UDB
UDB
Logic
HV
HV
B
A
Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C34
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
Fixed Function DRQs
Counters
Timer
Global
Clocks
Fixed Function IRQs
Figure 7-14
IO Port
Pins
CAN
UDB Array
EMIF
shows the structure of the IDMUX
I2C
Interrupt and DMA Processing in IDMUX
PSoC
Digital System Routing I/F
Digital System Routing I/F
IRQs
DRQs
UDB ARRAY
Del-Sig
Controller
Interrupt
®
3: CY8C34 Family
Detect
Detect
Edge
Edge
SC/CT
Blocks
Controller
DMA
DACs
0
1
2
0
1
2
3
Data Sheet
Page 46 of 127
DMA termout (IRQs)
IO Port
Pins
Comparators
Controller
Controller
Interrupt
DMA
Clocks
Global