CY8C34_1105 CYPRESS [Cypress Semiconductor], CY8C34_1105 Datasheet - Page 61

• Manufacturer Part Number: CY8C34_1105
• Description: Programmable System-on-Chip (PSoC) DC to 50 MHz operation
• Manufacturer: CYPRESS [Cypress Semiconductor]

9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can be
up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit transfers,
whichever is least. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, allowing these pins
to be used as General Purpose I/O (GPIO) instead. The JTAG interface is used for programming the flash memory, debugging, I/O
scan chains, and JTAG device chaining.
Document Number: 001-53304 Rev. *L
1
2
3
4
5
6
7
The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The
Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by V
level as host V
host Programmer.
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in
NVL is not equal to “Debug Ports Disabled”.
unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD
Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin
will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.
the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.
pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin
devices, but use dedicated XRES pin for rest of devices.
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by
By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is
nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as
If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES
Host Programmer
Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer
DD
. Rest of PSoC 3 voltage domains ( V
nTRST
TMS
XRES
GND
TDO
TDI
TCK
V
DD
5
6
V
DD
GND
DDD
, V
DDA
, V
DDIO0
DDIO1
, V
DDIO2
. So, V
, V
V
V
TMS (P1[0])
TDO (P1[3])
XRES or P1[2]
TDI (P1[4])
nTRST (P1[5])
SSD
TCK (P1[1]
DDD
DDIO3
DDIO1
, V
, V
) need not be at the same voltage level as
SSA
DDA
of PSoC 3 should be at same voltage
, V
DDIO0
5
PSoC
4, 7
PSoC 3
, V
6
DDIO1
, V
®
DDIO2
3: CY8C34 Family
, V
DDIO3
1, 2, 3, 4
Data Sheet
Page 61 of 127