CY8C34_1105 CYPRESS [Cypress Semiconductor], CY8C34_1105 Datasheet - Page 9

• Manufacturer Part Number: CY8C34_1105
• Description: Programmable System-on-Chip (PSoC) DC to 50 MHz operation
• Manufacturer: CYPRESS [Cypress Semiconductor]

Figure 2-5
analog performance on a two-layer board.
For information on circuit board layout issues for mixed signals, refer to the application note
Layout Considerations for PSoC® 3 and PSoC 5.
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in
Document Number: 001-53304 Rev. *L
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with capacitance added, as shown in
page 28. The trace between the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
Figure 2-6
and
Figure 2-6
Vssd
on page 10.
Figure 2-5. Example Schematic for 100-pin TQFP Part With Power Connections
on page 10 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
Vssd
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Vddd
Vssd
C6
0.1 uF
0.1 uF
C12
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
Vddd
Vssd
Vddd
Vssd
0.1 uF
C16
C1
1 uF
Vssd
Vddd
C2
0.1 uF
Vssd
C15
1 uF
Vccd
Vssa
10 uF, 6.3 V
OA0-, REF0, P0[3]
C13
kHzXout, P15[2]
kHzXin, P15[3]
OA0out, P0[1]
OA2out, P0[0]
OA3out, P3[7]
OA1out, P3[6]
OA0+, P0[2]
SIO, P12[3]
SIO, P12[2]
SIO, P12[1]
SIO, P12[0]
Vssa
Vddio0
C14
0.1 uF
U2
CY8C55xx
P4[1]
P4[0]
Vdda
Vssd
Vssa
Vcca
NC
NC
NC
NC
NC
NC
PSoC
Vddd
Vssd
AN57821 - Mixed Signal Circuit Board
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
0.1 uF
C11
Figure 2-5
®
Vssd
Vdda
Vssa
Vcca
Vddd
Vssd
3: CY8C34 Family
0.1 uF
C8
C9
1 uF
Vssd
Vssa
and
Vdda
Vssa
Vdda
Power System
1 uF
Data Sheet
C17
C10
0.1 uF
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