PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 113

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

10.5
Depending on the particular PIC18F2X20/4X20 device
selected, PORTE is implemented in two different ways.
For PIC18F4X20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/
AN7/CS) are individually configurable as inputs or out-
puts. These pins have Schmitt Trigger input buffers.
When selected as an analog input, these pins will read
as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISE
bit (= 0) will make the corresponding PORTE pin an
output (i.e., put the contents of the output latch on the
selected pin).
TRISE controls the direction of the RE pins even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/V
only pin. Its operation is controlled by the MCLRE con-
figuration
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
EXAMPLE 10-5:
 2003 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
Note:
PORTE, TRISE and LATE
Registers
PORTE
LATE
0x0A
ADCON1 ; for digital inputs
0x03
TRISC
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
bit
in
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
INITIALIZING PORTE
Configuration
PP
/RE3) is an input
Register
PIC18F2220/2320/4220/4320
3H
10.5.1
For PIC18F2X20 devices, PORTE is only available
when
(CONFIG3H<7> = 0). In these cases, PORTE is a
single bit, input only port comprised of RE3 only. The
pin operates as previously described.
FIGURE 10-13:
FIGURE 10-14:
Note 1:
MCLRE
Data Bus
RD TRISE
RD LATE
RD PORTE
High-Voltage Detect
Internal MCLR
RD LATE
Data
Bus
WR LATE
or
PORTE
WR TRISE
RD TRISE
To Analog Converter
RD PORTE
Master
I/O pins have diode protection to V
PORTE IN 28-PIN DEVICES
TRIS Latch
Data Latch
D
D
CK
CK
Clear
Q
Q
BLOCK DIAGRAM OF
RE2:RE0 PINS
BLOCK DIAGRAM OF
MCLR/V
functionality
Filter
Q
Q
Latch
Schmitt
Trigger
EN
EN
PP
D
EN
D
/RE3 PIN
Low-Level
MCLR Detect
DS39599C-page 111
Schmitt
Trigger
Input
Buffer
HV
DD
and V
is
MCLR/V
SS
disabled
I/O pin
RE3
.
PP
(1)
/