PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 186

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2220/2320/4220/4320
17.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (T
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one T
action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
FIGURE 17-20:
DS39599C-page 184
Note 1: If RSEN is programmed while any other
2: A bus collision during the Repeated Start
I
START CONDITION TIMING
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
2
event is in progress, it will not take effect.
condition occurs if:
C MASTER MODE REPEATED
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Falling edge of ninth clock,
BRG
BRG
REPEAT START CONDITION WAVEFORM
). When the Baud Rate Genera-
SDA
SCL
while SCL is high. Following
end of Xmit
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
BRG
2
C logic
. This
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
17.4.9.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note:
Sr = Repeated Start
T
BRG
At completion of Start bit,
hardware clears RSEN bit
Set S (SSPSTAT<3>)
and sets SSPIF
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Write to SSPBUF occurs here
WCOL Status Flag
T
BRG
1st bit
T
BRG
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