PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 222

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2220/2320/4220/4320
19.8
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
TABLE 19-2:
DS39599C-page 220
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend:
Note 1:
Name
(3)
(3)
2:
3:
4:
Use of the CCP2 Trigger
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
TRISA7
A/D Result Register High Byte
A/D Result Register Low Byte
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used for A/D conversion.
RE3 port bit is available only as an input pin when MCLRE bit in configuration register is ‘0’.
This register is not implemented on PIC18F2X20 devices.
These bits are not implemented on PIC18F2X20 devices.
These pins may be configured as port pins depending on the oscillator mode selected.
OSCFIF
OSCFIE
OSCFIP
PSPIF
PSPIE
PSPIP
RA7
ADFM
GIEH
Bit 7
GIE/
IBF
—
—
—
—
(4)
(4)
SUMMARY OF A/D REGISTERS
TRISA6
RA6
PEIE/
CMIF
CMIE
CMIP
GIEL
ADIF
ADIE
ADIP
Bit 6
OBE
—
—
—
—
—
(4)
(4)
TMR0IE
VCFG1
ACQT2
CHS3
RCIF
RCIE
RCIP
IBOV
Bit 5
RA5
—
—
—
—
—
PSPMODE
ACQT1
VCFG0
INT0IE
CHS3
EEIE
EEIP
Bit 4
TXIF
TXIE
TXIP
EEIF
RA4
—
—
PORTE Output Data Latch
PCFG3
ACQT0
SSPIE
SSPIP
RE3
SSPIF
BCLIF
BCLIE
BCLIP
CHS1
RBIE
Bit 3
RA3
—
(2)
Read PORTE pins, Write LATE
PORTE Data Direction
TMR0IF
CCP1IF
CCP1IE
CCP1IP
PCFG2
ADCS2
LVDIE
LVDIP
LVDIF
CHS0
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
Bit 2
RA2
ACQ
time, selected before the “special event trigger”,
GO/DONE
TMR2IE
TMR2IP
TMR3IE
TMR3IP
TMR2IF
TMR3IF
PCFG1
ADCS1
INT0IF
Bit 1
RA1
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
 2003 Microchip Technology Inc.
(4)
0000 0000
0000 0000
0000 0000
1111 1111
00-0 0000
00-0 0000
11-1 1111
xxxx xxxx
xxxx xxxx
--00 0000
--00 qqqq
0-00 0000
--0x 0000
--11 1111
xxxx xxxx
1111 1111
xxxx xxxx
---- xxxx
0000 -111
---- -xxx
POR, BOR
Value on
0000 0000
0000 0000
0000 0000
1111 1111
00-0 0000
00-0 0000
11-1 1111
uuuu uuuu
uuuu uuuu
--00 0000
--00 qqqq
0-00 0000
--0u 0000
--11 1111
uuuu uuuu
1111 1111
uuuu uuuu
---- uuuu
0000 -111
---- -uuu
Value on
all other
Resets