PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 154

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2220/2320/4220/4320
16.4.7
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DS39599C-page 152
Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISC and TRISD bits.
Set the PWM period by loading the PR2 register.
Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
• Select the polarities of the PWM output
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
For Half-Bridge Output mode, set the dead band
delay by loading PWM1CON<6:0> with the
appropriate value.
If auto-shutdown operation is required, load the
ECCPAS register:
• Select the auto-shutdown sources using the
• Select the shutdown states of the PWM
• Set the ECCPASE bit (ECCPAS<7>).
• Configure the comparators using the CMCON
• Configure the comparator inputs as analog
If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit
Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
• Clear the ECCPASE bit (ECCPAS<7>).
configurations and direction with the
P1M1:P1M0 bits.
signals with the CCP1M3:CCP1M0 bits.
ECCPAS<2:0> bits.
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
register.
inputs.
the TMR2IF bit (PIR1<1>).
T2CKPS bits (T2CON<1:0>).
(T2CON<2>).
pin outputs by clearing the respective TRISC
and TRISD bits.
SETUP FOR PWM OPERATION
16.4.8
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change.
In all other power managed modes, the selected power
managed mode clock will clock Timer2. Other power
managed mode clocks will most likely be different than
the primary clock frequency.
16.4.8.1
If
(CONFIG1H<6> is programmed), a clock failure will
force the device into the RC_RUN Power Managed
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source which may have a different clock
frequency than the primary clock. By loading the
IRCF2:IRCF0 bits on Resets, the user can obtain a
frequency higher than the default INTRC clock source
in the event of a clock failure.
See the previous section for additional details.
16.4.9
Both Power-on and subsequent Resets will force all
ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
the
Fail-Safe
OPERATION IN POWER MANAGED
MODES
EFFECTS OF A RESET
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
Clock
 2003 Microchip Technology Inc.
Monitor
is
enabled