PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 38

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2220/2320/4220/4320
3.4
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power operation. As the CPU is executing code in Run
modes, several additional exits from Run modes are
possible. They include exit to Sleep mode, exit to a cor-
responding Idle mode, and exit by executing a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT Reset.
3.4.1
The PRI_RUN mode is the normal full power execution
mode. If the SLEEP instruction is never executed, the
microcontroller operates in this mode (a SLEEP instruc-
tion is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
FIGURE 3-9:
DS39599C-page 36
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Run Modes
PRI_RUN MODE
SEC_RUN MODE
Q1
Q2
PC
Q3
Q4
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q1
1
2
3
Clock Transition
4
5
PC + 2
6
7
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
When a wake-up event occurs, the peripherals and
CPU continue to be clocked from the Timer1 oscillator
while the primary clock is started. When the primary
clock becomes ready, a clock switch back to the primary
clock occurs (see Figure 3-6). When the clock switch is
complete, the T1RUN bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is trig-
gered. The Timer1 oscillator will continue to run and
provide the system clock even though the T1OSCEN bit
is cleared. The primary clock is started. When the pri-
mary clock becomes ready, a clock switch back to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the pri-
mary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
Note:
8
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when try-
ing to set the SCS0 bit, the write to
SCS0 will not occur. If the Timer1 oscilla-
tor is enabled, but not yet running, system
clocks will be delayed until the oscillator
has started; in such situations, initial oscil-
lator operation is far from stable and
unpredictable operation may result.
Q2
Q3
 2003 Microchip Technology Inc.
Q4
Q1
PC + 2
Q2
Q3