PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 63

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

5.9.2
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
TABLE 5-1:
 2003 Microchip Technology Inc.
Legend: — = Unimplemented registers, read as ‘0’.
Note 1:
Address
FFDh
FFCh
FEEh POSTINC0
FEDh POSTDEC0
FECh
FEBh
FEAh
FFEh
FFBh
FEFh
FFFh
FFAh
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
2:
This register is not available on PIC18F2X20 devices.
This is not a physical register.
SPECIAL FUNCTION REGISTERS
PREINC0
PREINC1
PLUSW1
PLUSW0
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INDF0
INDF1
INTCON
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X20/4X20 DEVICES
Name
TOSU
TOSH
TOSL
BSR
PCL
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Address
FDDh POSTDEC2
FDCh
FCDh
FCCh
FDFh
FDEh POSTINC2
FDBh
FDAh
FCFh
FCEh
FCBh
FCAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
PIC18F2220/2320/4220/4320
PLUSW2
SSPCON1
SSPCON2
WDTCON
OSCCON
SSPSTAT
ADRESH
ADCON0
ADCON1
ADCON2
LVDCON
SSPBUF
SSPADD
ADRESL
INDF2
STATUS
TMR0H
T0CON
TMR1H
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
PR2
—
(2)
(2)
(2)
(2)
(2)
Address
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
FBDh
FBCh
FBAh
FBEh
FBBh
FADh
FACh
FBFh
FB9h
FB8h
FB7h PWM1CON
FB6h
FB5h
FB4h
FB3h
FB1h
FB0h
FAFh
FAEh
FABh
FAAh
FB2h
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
ECCPAS
CCP1CON
CCP2CON
CVRCON
CCPR1H
CCPR2H
EECON2
EECON1
CCPR1L
CCPR2L
CMCON
EEDATA
SPBRG
RCREG
TMR3H
T3CON
TXREG
EEADR
TMR3L
RCSTA
TXSTA
Name
IPR2
PIR2
PIE2
—
—
—
—
—
—
—
(1)
(1)
Address
F9Eh
F9Dh
F9Ch
F9Bh
F8Dh
F8Ch
F8Ah
F9Fh
F9Ah
F8Fh
F8Eh
F8Bh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
DS39599C-page 61
OSCTUNE
PORTD
TRISD
TRISE
LATE
LATD
PORTE
PORTC
PORTB
PORTA
TRISC
TRISB
TRISA
Name
LATC
LATB
LATA
IPR1
PIR1
PIE1
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)