PIC18F2331-E/ML MICROCHIP [Microchip Technology], PIC18F2331-E/ML Datasheet - Page 214

• Manufacturer Part Number: PIC18F2331-E/ML
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2331/2431/4331/4431
19.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
FIGURE 19-6:
DS39616D-page 214
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
A7 A6 A5 A4 A3 A2 A1
1
Reception
2
Receiving Address
3
4
I
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
R/W = 0
7
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
4
SSPOV bit is set because the SSPBUF register is still full
D3
5
D2
6
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
 2010 Microchip Technology Inc.
ACK is not sent
D3
5
D2
6
D1
7
D0
8
ACK
9
Bus master
terminates
transfer
P