PIC18F2331-E/ML MICROCHIP [Microchip Technology], PIC18F2331-E/ML Datasheet - Page 280

• Manufacturer Part Number: PIC18F2331-E/ML
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2331/2431/4331/4431
23.5.1
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit set to ‘0’, a table read instruction that executes from
within that block is allowed to read. A table read instruc-
tion that executes from a location outside of that block is
not allowed to read, and will result in reading ‘0’s.
Figures
read protection.
FIGURE 23-6:
DS39616D-page 280
Results: All table writes are disabled to Blockn whenever WRTn = 0
TBLPTR = 0002FFh
23-6
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 0007FEh
PC = 0017FEh
through
23-8
TABLE WRITE (WRTn) DISALLOWED
illustrate table write and table
Program Memory
TBLWT *
TBLWT *
Note:
0017FFh
001800h
000000h
0001FFh
000200h
0007FFh
000800h
000FFFh
001000h
001FFFh
.
Code protection bits may only be written
to a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
 2010 Microchip Technology Inc.