PIC18F2331-E/ML MICROCHIP [Microchip Technology], PIC18F2331-E/ML Datasheet - Page 263
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PIC18F2331-E/ML
Manufacturer Part Number
PIC18F2331-E/ML
Description
28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2331-EML.pdf
(392 pages)
- Current page: 263 of 392
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23.0
PIC18F2331/2431/4331/4431 devices include several
features intended to maximize system reliability and min-
imize cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in
“Oscillator
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2331/2431/4331/
4431 devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits, or
software-controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
2010 Microchip Technology Inc.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
SPECIAL FEATURES OF THE
CPU
Configurations”.
Section 3.0
PIC18F2331/2431/4331/4431
23.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
Configuration register. In normal operation mode, a
TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to
to Flash Program
Configuration Bits
Memory”.
Section 8.5 “Writing
DS39616D-page 263
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