PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 171

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

15.4
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP1 pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.4
“Setup for PWM Operation”.
FIGURE 15-3:
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
 2004 Microchip Technology Inc.
Note 1: The 8-bit TMR2 value is concatenated with 2-bit inter-
Note:
CCPR1H (Slave)
CCPR1L
Comparator
Duty Cycle Registers
TMR2
PR2
Comparator
PWM Mode
nal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
Clearing the CCP1CON register will force
the RC2 output latch (depending on
device configuration) to the default low
level. This is not the PORTC I/O data
latch.
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
R
S
Q
TRISC<2>
RC2/CCP1
PORTC<2>
PIC18F2480/2580/4480/4580
Preliminary
FIGURE 15-4:
15.4.1
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using the following formula.
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TMR1 (TMR3) is equal to PR2 (PR2), the
following three events occur on the next increment
cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from ECCPR1L
15.4.2
The PWM duty cycle is specified by writing to the
ECCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The ECCPR1L con-
tains the eight MSbs and the CCP1CON<5:4> contains
the two LSbs. This 10-bit value is represented by
ECCPR1L:ECCP1CON<5:4>. The following equation
is used to calculate the PWM duty cycle in time.
EQUATION 15-2:
ECCPR1L and ECCP1CON<5:4> can be written to at
any time, but the duty cycle value is not latched into
ECCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
ECCPR1H is a read-only register.
PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4>) •
cycle = 0%, the CCP1 pin will not be set)
into ECCPR1H
Note:
TMR2 = PR2
PWM Period = (PR2) + 1] • 4 • T
Duty Cycle
PWM PERIOD
The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
Period
TMR2 = Duty Cycle
T
OSC
PWM OUTPUT
(TMR2 Prescale Value)
• (TMR2 Prescale Value)
TMR2 = PR2
DS39637A-page 169
OSC
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