PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 73

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

5.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 5-1:
 2004 Microchip Technology Inc.
Note 1:
Address
FEDh
FECh
FFDh
FFCh
FEEh
FEBh
FEAh
FFEh
FFBh
FEFh
FFFh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
2:
3:
4:
RE3 bit only available when MCLRE = 0; otherwise, the bit reads as ‘0’.
Bits and registers available only when ENPORTS = 1; otherwise, the registers/bits read as ‘0’.
When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
This is not a physical register.
SPECIAL FUNCTION REGISTERS
POSTDEC0
POSTDEC1
POSTINC0
POSTINC1
PREINC0
PREINC1
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2480/2580/4480/4580 DEVICES
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
Name
TOSU
TOSH
TOSL
BSR
PCL
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Address
FDEh
FDDh
FDCh
FCDh
FCCh
FDFh
FDBh
FDAh
FCFh
FCEh
FCBh
FCAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PIC18F2480/2580/4480/4580
POSTDEC2
POSTINC2
PREINC2
PLUSW2
HLVDCON
SSPCON1
SSPCON2
WDTCON
OSCCON
SSPSTAT
ADRESH
ADCON0
ADCON1
ADCON2
SSPADD
ADRESL
INDF2
SSPBUF
STATUS
TMR0H
T0CON
TMR1H
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
PR2
Preliminary
—
(4)
(4)
(4)
(4)
(4)
Address
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s Status register is described later in this section.
Registers related to the operation of a peripheral
feature are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
FBDh
FBCh
FBFh
FBEh
FBBh
FBAh
FAEh
FADh
FACh
FABh
FAAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
ECCP1CON
ECCP1AS
ECCP1DEL
CVRCON
CCPR2H
EECON2
CCPR2L
BAUDCON
ECCPR1H
CCP1CON
ECCPR1L
CMCON
SPBRGH
EECON1
EEDATA
RCREG
TMR3H
SPBRG
TXREG
EEADR
TMR3L
T3CON
RCSTA
TXSTA
Name
IPR3
PIR3
IPR2
PIR2
PIE3
PIE2
—
—
(1)
(2)
(2)
(4)
(2)
(2)
(2)
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h
F98h
F97h
F96h
F95h
F94h
F92h
F91h
F90h
F8Fh
F89h
F88h
F87h
F84h
F82h
F81h
F80h
F93h
F86h
F85h
F83h
DS39637A-page 71
OSCTUNE
PORTD
TRISE
TRISD
PORTC
LATE
LATD
PORTE
PORTB
PORTA
TRISC
TRISB
TRISA
Name
LATC
LATB
LATA
IPR1
PIR1
PIE1
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)