PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 213

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

17.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
set or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code con-
ducts all I
conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 17-16:
 2004 Microchip Technology Inc.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
SDA
SCL
2
C bus operations based on Start and Stop bit
MASTER MODE
to
2
C bus may be taken when the P bit is
the
2
C port to receive data.
SSPBUF
MSSP BLOCK DIAGRAM (I
SDA In
register
Bus Collision
SCL In
initiating
Read
PIC18F2480/2580/4480/4580
MSb
Write Collision Detect
Preliminary
Start bit, Stop bit,
end of XMIT/RCV
State Counter for
Clock Arbitration
Start bit Detect
Acknowledge
Stop bit Detect
SSPBUF
2
Generate
SSPSR
C™ MASTER MODE)
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
LSb
Note:
Write
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
C Master mode, does not allow queueing
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS39637A-page 211