HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 100

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Handling
5.5
5.5.1
Exception handling can be triggered by the trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Table 5.9
Note:
5.5.2
When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The CPU reads the start address of the exception handling routine from the exception handling
Rev. 4.00 Sep. 13, 2007 Page 74 of 502
REJ09B0239-0400
Type
Trap instruction
Illegal slot
instructions*
General illegal
instructions*
instruction to be executed after the TRAPA instruction.
vector table that corresponds to the vector number specified in the TRAPA instruction,
program execution branches to that address, and then the program starts. This branch is not a
delayed branch.
*
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Trap Instructions
The operation is not guaranteed when undefined instructions other than H'FC00 to
H'FFFF are decoded.
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot) or
instructions that changes the PC
value
Undefined code anywhere
besides in a delay slot
Comment

Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that changes the PC value:
JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
TRAPA, BF/S, BT/S, BSRF, BRAF, LDC
Rm,SR, LDC.L @Rm+,SR
