HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 24

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Table 7.13
Table 7.14
Table 7.15
Table 7.16
Table 7.17
Section 8 Clock Pulse Generator (CPG)
Table 8.1
Table 8.2
Table 8.3
Section 10 Power-Down Modes
Table 10.1
Table 10.2
Table 10.3
Section 12 Serial Communication Interface with FIFO (SCIF)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.9
Table 12.10
Table 12.11
Rev. 4.00 Sep. 13, 2007 Page xxiv of xxvi
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) .......................................................................................... 262
Address Map 1 (CMNCR.MAP = 0) .................................................................... 112
Address Map 2 (CMNCR.MAP = 1) .................................................................... 113
Correspondence between External Pin (MD3), Memory Type,
and Bus Width for CS0......................................................................................... 114
Correspondence between External Pin (MD5) and Endians................................. 114
16-Bit External Device/Big Endian Access and Data Alignment......................... 144
8-Bit External Device/Big Endian Access and Data Alignment........................... 145
16-Bit External Device/Little Endian Access and Data Alignment ...................... 146
8-Bit External Device/Little Endian Access and Data Alignment ........................ 147
Relationship between Register Settings and Address Multiplex Output (1)......... 157
Relationship between Register Settings and Address Multiplex Output (2)......... 158
Relationship between Register Settings and Address Multiplex Output (3)......... 159
Relationship between Register Settings and Address Multiplex Output (4)......... 160
Relationship between Register Settings and Address Multiplex Output (5)......... 161
Relationship between Register Settings and Address Multiplex Output (6)......... 162
Relationship between Access Size and Number of Bursts.................................... 163
Access Address for SDRAM Mode Register Write.............................................. 179
Pin Configuration.................................................................................................. 196
Mode Control Pins and Clock Operating Modes .................................................. 196
Possible Combination of Clock Modes and FRQCR Values................................ 197
States of Power-Down Modes .............................................................................. 214
Pin Configuration.................................................................................................. 215
Register States in Software Standby Mode........................................................... 221
SCIF Pins.............................................................................................................. 238
SCSMR Settings ................................................................................................... 258
Bit Rates and SCBRR Settings in Asynchronous Mode....................................... 258
Bit Rates and SCBRR Settings in Synchronous Mode ......................................... 261
Maximum Bit Rates with External Clock Input (Asynchronous Mode)............... 263
Maximum Bit Rates with External Clock Input (Synchronous Mode) ................. 263
SCSMR Settings and SCIF Communication Formats .......................................... 274
SCSMR and SCSCR Settings and SCIF Clock Source Selection......................... 274
Serial Communication Formats (Asynchronous Mode).................................... 276
SCIF Interrupt Sources ..................................................................................... 294