HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 256

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Compare Match Timer (CMT)
11.4
11.4.1
The CMT has channels and each of them to which a different vector address is allocated has
compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 6, Interrupt Controller (INTC).
11.4.2
When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in
CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values
match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR
and CMCNT, the compare match signal is not generated until the next CMCNT counter clock
input. Figure 11.4 shows the timing of CMF bit setting.
11.4.3
The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0.
Rev. 4.00 Sep. 13, 2007 Page 230 of 502
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Interrupts
Interrupt Sources
Timing of Setting Compare Match Flag
Timing of Clearing Compare Match Flag
Peripheral operating
Compare match
Counter clock
clock (Pφ)
CMCOR1
CMCNT1
signal
Figure 11.4 Timing of CMF Setting
(N + 1)th
N
N
clock
0