HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 92

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Handling
5.1.2
The exceptions are detected and the exception handling starts according to the timing shown in
table 5.2.
Table 5.2
When exception handling starts, the CPU operates
Exception Handling Triggered by Reset: The initial values of the program counter (PC) and
stack pointer (SP) are fetched from the exception handling vector table (PC from the address
H'A0000000 and SP from the address H'A0000004). For details, see section 5.1.3, Exception
Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F
(B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program
starts from the PC address fetched from the exception handling vector table.
Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are
saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is
written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception
handling, bits I3 to I0 are not affected. The start address is then fetched from the exception
handling vector table and the program starts from that address.
Rev. 4.00 Sep. 13, 2007 Page 66 of 502
REJ09B0239-0400
Exception
Reset
Address error
Interrupt
Instruction
Exception Handling Operations
Timing for Exception Detection and Start of Exception Handling
Power-on reset
H-UDI reset
Trap instruction
General illegal
instructions
Illegal slot
instructions
Timing of Source Detection and Start of Exception Handling
Started when the RES pin changes from low to high or when the
WDT overflows.
Started when the reset assert command and the reset negate
command are input to the H-UDI in this order.
Detected during the instruction decode stage and started after the
execution of the current instruction is completed.
Started by the execution of the TRAPA instruction.
Started when an undefined code placed at other than a delay slot
(immediately after a delayed branch instruction) is decoded.
Started when an undefined code placed at a delay slot
(immediately after a delayed branch instruction) or an instruction
that changes the PC value is detected.