HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 17

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 1 Overview
Figure 1.1 Block Diagram .............................................................................................................. 5
Figure 1.2 Pin Assignments ............................................................................................................ 6
Section 2 CPU
Figure 2.1 CPU Internal Register Configuration .......................................................................... 20
Figure 2.2 Register Data Format................................................................................................... 24
Figure 2.3 Memory Data Format .................................................................................................. 24
Figure 2.4 CPU State Transition................................................................................................... 48
Section 3 Cache
Figure 3.1 Cache Structure ........................................................................................................... 51
Figure 3.2 Cache Search Scheme ................................................................................................. 56
Figure 3.3 Write-Back Buffer Configuration................................................................................ 58
Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access............................. 60
Section 6 Interrupt Controller (INTC)
Figure 6.1 INTC Block Diagram .................................................................................................. 82
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................... 99
Figure 6.3 Interrupt Sequence Flowchart.................................................................................... 103
Figure 6.4 Stack after Interrupt Exception Handling .................................................................. 104
Section 7 Bus State Controller (BSC)
Figure 7.1 Block Diagram of BSC.............................................................................................. 109
Figure 7.2 Address Space ........................................................................................................... 112
Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)............................................ 148
Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 Bits,
Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 Bits,
Figure 7.6 Example of 16-Bit Data-Width SRAM Connection .................................................. 151
Figure 7.7 Example of 8-Bit Data-Width SRAM Connection.................................................... 151
Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only) ................................. 152
Figure 7.9 Wait Cycle Timing for Normal Space Access
Figure 7.10 Example of Timing When CSn Assertion Period is Extended ................................ 154
Figure 7.11 Example of 16-Bit Data-Width SDRAM Connection ............................................. 156
Figure 7.12 Burst Read Basic Timing (Auto Precharge) ............................................................ 164
Figure 7.13 Burst Read Wait Specification Timing (Auto Precharge) ....................................... 165
Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0).............. 149
(Wait Cycle Insertion Using WAIT) ......................................................................... 153
Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0).............. 150
Figures
Rev. 4.00 Sep. 13, 2007 Page xvii of xxvi