HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 226

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Clock Pulse Generator (CPG)
8.5
The internal clock frequency can be changed by changing the multiplication ratio of PLL circuit 1.
The peripheral clock frequency can be changed either by changing the multiplication ratio of PLL
circuit 1 or by changing the division ratio of divider 1. All of these are controlled by software
through the frequency control register. The methods are described below.
8.5.1
The PLL lock time must be preserved when the multiplication ratio of PLL circuit 1 is changed.
The on-chip WDT counts for preserving the PLL lock time.
1. In the initial state, the multiplication ratio of PLL circuit 1 is 1.
2. Set a value that satisfies the given PLL lock time in the WDT and stop the WDT. The
3. Set the desired value in bits STC2 to STC0 while the MDCHG bit in STBCR is 0. The division
4. This LSI pauses internally and the WDT starts incrementing. The internal and peripheral
5. Supply of the specified clock starts at a WDT count overflow, and this LSI starts operating
Rev. 4.00 Sep. 13, 2007 Page 200 of 502
REJ09B0239-0400
Bit
2
1
0
following must be set.
 TME bit in WTCSR = 0: WDT stops
 Bits CKS2 to CKS0 in WTCSR: Division ratio of WDT count clock
 WTCNT: Initial counter value
ratio can also be set in bits PFC2 to PFC0.
clocks both stop and only the WDT is supplied with the clock. The clock will continue to be
output on the CKIO pin.
again. The WDT stops after it overflows.
Changing Frequency
Changing Multiplication Ratio
Bit Name
PFC2
PFC1
PFC0
Initial
Value
0
1
1
R/W
R/W
R/W
R/W
Description
Peripheral Clock Frequency Division Ratio
Specify the division ratio of the peripheral clock
frequency with respect to the output frequency of PLL
circuit 1.
000: ×1
001: ×1/2
011: ×1/4
Other values: Setting prohibited