CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 22

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

8.9
8.10
8.11
22
TSLIP1
TSLIP0
7
7
0
7
0
0
Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
Interrupt 2 Mask (0Ch)
Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge ac-
tive mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge ac-
tive mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode,
the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Ac-
tice High or Low) only depends on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error
is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit
is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status
register. The bit positions align with the corresponding bits in Interrupt 2 register. This register defaults
to 00h.
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge ac-
tive mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge ac-
tive mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode,
the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Ac-
tive High or Low) only depends on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
6
0
0
6
0
6
0
0
5
0
0
5
0
5
0
0
4
0
0
4
4
0
0
0
3
0
0
3
0
3
0
0
EFTUM
EFTU1
EFTU0
2
2
2
0
0
EFTC1
EFTC0
1
1
1
0
0
0
CS8405A
DS469F2
0
0
0
0
0
0
0
0