CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 23

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

8.12
Note:
8.13
DS469F2
7
0
7
0
Channel Status Data Buffer Control (12h)
User Data Buffer Control (13h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
There are separate complete buffers for the Channel Status and User bits. This control bit determines which
buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
CAM - C-data buffer control port access mode bit
UD - User bit data source specifier
UBM1:0 - Sets the operating mode of the AES3 User bit manager
EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
Default = ‘0’
0 - One byte mode
1 - Two byte mode
Default = ‘0’
0 - The U pin is an input. The User bit data is latched in on both rising and falling edges of
1 - Sets the U data buffer as the source of transmitted U data. The U pin also becomes an
Default = ‘00’
00 - Transmit all zeros mode
01 - Block mode
10 - Reserved
11 - Reserved
Default = ‘0’
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfer
OLRCK. This setting also chooses the U pin as the source for transmitted U data.
indeterminate output.
6
6
0
0
BSEL
5
5
0
UD
4
4
0
UBM1
3
0
3
EFTCI
UBM0
2
2
CAM
1
1
0
CS8405A
EFTUI
0
0
0
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