CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 36

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

15.1.2 Serial Copy Management System
In software mode, the CS8405A allows read/mod-
ify/write access to all the channel status bits. For
consumer mode SCMS compliance, the host mi-
crocontroller needs to manipulate the Category
Code, Copy bit and L bit appropriately.
In hardware mode, the SCMS protocol can be fol-
lowed by either using the COPY and ORIG input
pins, or by using the C bit serial input pin. These
options are documented in the hardware mode
section of this data sheet.
15.1.3 Channel Status Data E Buffer
The E buffer is organized as 24 x 16-bit words. For
each word the MS Byte is the A channel data, and
the LS Byte is the B channel data (see Figure 14).
There are two methods of accessing this memory,
known as one byte mode and two byte mode. The
desired mode is selected through a control register
bit.
15.1.3.1 One Byte mode
In many applications, the channel status blocks for
the A and B channels will be identical. In this situ-
ation, if the user reads a byte from one of the chan-
nel's blocks, the corresponding byte for the other
channel will be the same. Similarly, if the user
wrote a byte to one channel's block, it would be
necessary to write the same byte to the other
block. One byte mode takes advantage of the often
identical nature of A and B channel status data.
When reading data in one byte mode, a single byte
is returned, which can be from channel A or B data,
depending on a register control bit. If a write is be-
ing done, the CS8405A expects a single byte to be
input to its control port. This byte will be written to
both the A and B locations in the addressed word.
One byte mode saves the user substantial control
port access time, as it effectively accesses 2 bytes
worth of information in 1 byte's worth of access
time. If the control port's auto increment address-
36
(SCMS)
Access
ing is used in combination with this mode, multi-
byte accesses such as full-block reads or writes
can be done especially efficiently.
15.1.3.2 Two Byte mode
There are those applications in which the A and B
channel status blocks will not be the same, and the
user is interested in accessing both blocks. In
these situations, two byte mode should be used to
access the E buffer.
In this mode, a read will cause the CS8405A to out-
put two bytes from its control port. The first byte out
will represent the A channel status data, and the
2nd byte will represent the B channel status data.
Writing is similar, in that two bytes must now be in-
put to the CS8405A's control port. The A channel
status data is first, B channel status data second.
15.2
The CS8405A U bit manager has two operating
modes:
Mode 1. Transmit all zeros.
Mode 2. Block mode.
15.2.1 Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the
output U data, regardless of E buffer contents. This
mode is intended for the user who wants the output
U channel to contain no data.
15.2.2 Mode 2: Block Mode
Mode 2 is very similar to the scheme used to control
the C bits. Entire blocks of U data are buffered using
2 block-sized RAMs to perform the buffering. The
user has access to the first buffer, denoted the E buff-
er, through the control port. It is the only mode in
which the user can merge his own U data into the
transmitted AES3 data stream. The U buffer access
only operates in two byte mode, since there is no con-
cept of A and B blocks for user data. The arrange-
ment
Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0]
Bit0[B0]. The arrangement of the data in each byte is
that the MSB is the first transmitted bit. The bit for the
A subframe is followed by the bit for the B subframe.
AES3 User (U) Bit Management
of
the
data
is
CS8405A
as
DS469F2
follows: