IS42S16100-10TI ISSI [Integrated Silicon Solution, Inc], IS42S16100-10TI Datasheet - Page 27

• Manufacturer Part Number: IS42S16100-10TI
• Description: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS42S16100
Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
CAS latency = 2, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
11/01/01
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding to
the new write command can be input in place of the data
for the previous write command.
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
CLK
I/O
CLK
I/O
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
t
CCD
D
IN
t
CCD
B0
D
OUT
D
A0
IN
1-800-379-4774
B1
D
OUT
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two read command (t
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
B0
IN
B2
D
OUT
D
B1
IN
B3
D
OUT
B2
D
OUT
B3
ISSI
CCD
CCD
) must be at
) must be
27
®