IS42S16100-10TI ISSI [Integrated Silicon Solution, Inc], IS42S16100-10TI Datasheet - Page 34

• Manufacturer Part Number: IS42S16100-10TI
• Description: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

34
IS42S16100
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burst data input can be temporarily interrupted (muted )
during a write cycle using the U/LDQM pins. Regardless of
the CAS latency, as soon as one of the U/LDQM pins goes
HIGH, the corresponding externally applied input data will
no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.
The IS42S16100 will revert to accepting input as soon as
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the
burst read cycle operates normally, but the write cycle only
writes a single data item for each write cycle. The CAS
latency and DQM latency are the same as in normal mode.
CAS latency = 2, burstlength = 4
CAS latency = 2, 3
COMMAND
COMMAND
I/O8-I/O15
I/O0-I/O7
UDQM
LDQM
CLK
CLK
I/O
WRITE (CA=A, BANK 0)
DATA MASK (UPPER BYTE)
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
WRITE A0
WRITE A0
D
Integrated Silicon Solution, Inc. — www.issi.com —
D
t
IN
DMD=0
IN
A0
A0
D
IN
that pin is dropped to LOW and data will be written to the
device. This input control operates independently on a byte
basis with the UDQM pin controlling upper byte input (pin
I/O8 to I/O15) and the LDQM pin controlling the lower byte
input (pins I/O0 to I/O7).
Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, inparticular,
incrementing of the internal burst counter continues.
A1
D
IN
A2
D
D
IN
IN
A3
A3
ISSI
1-800-379-4774
Don't Care
11/01/01
Rev. C
®