IS42S16100-10TI ISSI [Integrated Silicon Solution, Inc], IS42S16100-10TI Datasheet - Page 32

• Manufacturer Part Number: IS42S16100-10TI
• Description: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

32
IS42S16100
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100 can output data continuously from the
burst start address (a) to location a+255 during a read cycle
in which the burst length is set to full page. The IS42S16100
repeats the operation starting at the 256th cycle with the
data output returning to location (a) and continuing with
a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
must be executed within the ACT to PRE command period
(t
CAS latency = 3, burstlength = 4
RAS
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
max.) following the burst stop command.
CLK
CLK
I/O
I/O
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
READ A0
READ A0
D
OUT
A0 D
Integrated Silicon Solution, Inc. — www.issi.com —
D
OUT
OUT
A0
A0 D
After the period (t
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (t
CAS latency is two and three clock cycle when the CAS
latency is three.
D
OUT
OUT
CAS
CAS
CAS
CAS
CAS Latency
A1
A0
BURST STOP
BURST STOP
t
RBD
D
D
OUT
OUT
BST
BST
A2
RBD
A1
RBD
) required for burst data output to
t
RBD
D
D
) is two clock cycle when the
OUT
OUT
t
RBD
A3
A2
3
3
D
OUT
HI-Z
A3
ISSI
1-800-379-4774
HI-Z
2
2
11/01/01
Rev. C
®