IS42S16100-10TI ISSI [Integrated Silicon Solution, Inc], IS42S16100-10TI Datasheet - Page 29

• Manufacturer Part Number: IS42S16100-10TI
• Description: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS42S16100
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
11/01/01
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding to
the new write command can be input at the point new
write command is executed. To prevent collision
between input and output data at the I/On pins during
this operation, the
CAS latency = 2, 3, burstlength = 4
COMMAND
U/LDQM
CLK
I/O
READ (CA=A, BANK 0)
READ A0
HI-Z
D
WRITE B0
IN
t
CCD
B0
WRITE (CA=B, BANK 0)
D
IN
B1
1-800-379-4774
D
output data must be masked using the U/LDQM pins. The
interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
IN
B2
CCD
D
IN
) between these commands must be at least
B3
ISSI
29
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