CY14E256LA-ZS25XI CYPRESS [Cypress Semiconductor], CY14E256LA-ZS25XI Datasheet - Page 10

• Manufacturer Part Number: CY14E256LA-ZS25XI
• Description: 256 Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

AC Switching Characteristics
Switching Waveforms
Notes
SRAM Read Cycle
t
t
t
t
t
t
t
t
t
t
t
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
ACE
RC
AA
DOE
OHA
LZCE
HZCE
LZOE
HZOE
PU
PD
WC
PWE
SCE
SD
HD
AW
SA
HA
HZWE
LZWE
11. WE must be HIGH during SRAM read cycles.
12. Device is continuously selected with CE and OE LOW.
13. Measured ±200 mV from steady state output voltage.
14. If WE is low when CE goes low, the outputs remain in the high impedance state.
15. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-54952 Rev. *B
[12]
[11]
[10]
[10]
Parameters
[12]
Cypress
[10, 13]
[10, 13]
[10, 13]
[10, 13]
[10, 13]
[10, 13,14]
Data Output
Parameters
Address
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
WC
WP
CW
DW
DH
AW
AS
WR
WZ
OW
Parameters
Alt
Figure 4. SRAM Read Cycle #1: Address Controlled
Previous Data Valid
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
t
Description
OHA
Address Valid
t
AA
t
RC
Min
25
25
20
20
10
20
3
3
0
0
0
0
0
3
25 ns
[11, 12, 15]
Output Data Valid
Max
25
25
12
10
10
25
10
Min
45
45
30
30
15
30
0
0
3
3
0
0
0
3
45 ns
CY14E256LA
Max
15
15
45
15
45
45
20
Unit
Page 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback