CY14E256LA-ZS25XI CYPRESS [Cypress Semiconductor], CY14E256LA-ZS25XI Datasheet - Page 3

• Manufacturer Part Number: CY14E256LA-ZS25XI
• Description: 256 Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pinouts
Table 1. Pin Definitions
Document Number: 001-54952 Rev. *B
Notes
DQ
1. Address expansion for 1 Mbit. NC pin not connected to die
2. Address expansion for 2 Mbit. NC pin not connected to die.
3. Address expansion for 4 Mbit. NC pin not connected to die.
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Pin Name
A
NC
0
V
DQ
DQ
DQ
HSB
DQ
0
NC
NC
V
V
WE
V
V
WE
CE
OE
NC
NC
– A
CE
A
CAP
A
A
CC
SS
A
A
– DQ
CC
A
A
SS
A
A
A
[5]
8
9
7
5
6
0
1
0
1
2
3
2
3
4
14
10
11
12
13
14
16
17
18
19
7
1
2
3
4
5
6
7
8
9
15
20
21
22
Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
No Connect No Connect. This pin is not connected to the die.
(not to scale)
I/O Type
Ground
44 - TSOP II
Supply
Supply
Power
Power
Input
Input
Input
Input
Top View
(x8)
Address Inputs Used to Select One of the 32,768 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE HIGH.
Ground for the Device. Must be connected to the ground of the system.
Power Supply Inputs to the Device.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
38
23
44
43
42
39
37
36
35
33
32
31
30
29
28
25
24
41
40
34
27
26
HSB
OE
Figure 1. Pin Diagram - 44 Pin TSOP II/32 Pin SOIC
NC
DQ
DQ
V
A
NC
NC
NC
NC
V
DQ
DQ
V
A
A
A
A
NC
NC
NC
SS
14
CC
11
CAP
13
12
10
[4]
[3]
[2]
7
6
4
5
[1]
[1]
Description
(not to scale)
32 - SOIC
Top View
(x8)
CY14E256LA
Page 3
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