CY14E256LA-ZS25XI CYPRESS [Cypress Semiconductor], CY14E256LA-ZS25XI Datasheet - Page 5

• Manufacturer Part Number: CY14E256LA-ZS25XI
• Description: 256 Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

During any STORE operation, regardless of how it is initiated,
the CY14E256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the CY14E256LA remains disabled until the
HSB pin returns HIGH. Leave the HSB unconnected if it is not
used.
Hardware RECALL (Power Up)
During
(V
V
cycle is automatically initiated and takes t
During this time, HSB is driven low by the HSB driver.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14E256LA Software
STORE cycle is initiated by executing sequential CE controlled
read cycles from six specific address locations in exact order.
During the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
Table 2. Mode Selection
Document Number: 001-54952 Rev. *B
Notes
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0FC0 Initiate STORE Cycle
6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
CC
CC
< V
again exceeds the sense voltage of V
CE
SWITCH
H
L
L
L
power
), an internal RECALL request is latched. When
up
or
after
WE
X
H
H
L
any
low
HRECALL
SWITCH
power
OE
X
X
L
L
, a RECALL
to complete.
condition
A
0x3C1F
0x0E38
0x31C7
0x03E0
0x303F
0x0B45
14
- A
X
X
X
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
activated again for the read and write operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
0
[6]
Not Selected
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Write SRAM
AutoStore
Disable
Mode
STORE
RECALL
Output High-Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
cycle time is fulfilled, the SRAM is
Input Data
cycle time, the SRAM is again
I/O
CY14E256LA
Standby
Active
Power
Active
Active
[7]
Page 5
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