HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 11

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Field
BT
BL
Field
BA1
BA0
Qoff
DQS
OCD
Program
rounding up to the next integer: WR [cycles] ≥ t
for the analogue t
Bits
3
[2:0]
Bits
14
13
12
10
[9:7]
Type
w
w
Type
reg. addr.
w
WR
timing WR
1)
1)
MIN
Description
Burst Type
0
1
Burst Length
Note: All other bit combinations are illegal.
010
011
Description
Bank Address [1]
0
Bank Address [0]
1
Output Disable
0
1
Complement Data Strobe (DQS Output)
0
1
Off-Chip Driver Calibration Program
000
001
010
100
111
B
B
is determined by t
B
B
B
B
B
B
B
B
B
B
B
B
B
BT Sequential
BT Interleaved
BL 4
BL 8
BA1 Bank Address
BA0 Bank Address
QOff Output buffers enabled
QOff Output buffers disabled
DQS Enable
DQS Disable
OCD OCD calibration mode exit, maintain setting
OCD Drive (1)
OCD Drive (0)
OCD Adjust mode
OCD OCD calibration default
WR
(ns) / t
CK.MAX
CK
(ns). The mode register must be programmed to fulfill the minimum requirement
and WR
11
MAX
Extended Mode Register Definition (BA[1:0] = 01B)
is determined by t
512-Mbit Double-Data-Rate-Two SDRAM
CK.MIN
.
HYB18T512161B2F–20/25
WR
Internet Data Sheet
(in ns) by t
TABLE 7
CK
(in ns) and