HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 3

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and
describes its main characteristics.
1.1
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V
• 1.8 V
• DRAM organizations with 16 data in/outputs
• Double Data Rate architecture:
• Programmable CAS Latency: 3, 4, 5, 6, 7
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
• Commands entered on each positive clock edge, data and
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Product Number
HYB18T512161B2F–20/25
– two data transfers per clock cycle
– four internal banks for concurrent operation
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
operation
data mask are referenced to both edges of DQS
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
±
±
0.1V V
0.1V V
DD
DDQ
for [–20/–25]
Overview
Features
for [–20/–25]
Org.
×16
3
Ordering Information for RoHS compliant products
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
• Off-Chip-Driver impedance adjustment (OCD) and On-
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
• Average Refresh Period 7.8 μs at a
• Full Strength and reduced Strength (60%) Data-Output
• 2kB page size
• Packages: P-TFBGA-84
• RoHS Compliant Products
Clock (MHz)
500/400
command and data bus efficiency
Die-Termination (ODT) for better signal quality.
Down modes
°C, 3.9 μs between 85 °C and 95 °C
Drivers
512-Mbit Double-Data-Rate-Two SDRAM
1)
HYB18T512161B2F–20/25
Package
P-TFBGA-84
Internet Data Sheet
T
CASE
lower than 85
TABLE 1