HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 13

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) w = write only
2) When DRAM is operated at 85°C ≤
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
1) w = write only
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Field
Partial Self Refresh for 4 banks
PASR [2:0]
Field
BA1
BA0
A
Input Pin
DQ[7:0]
DQ[15:8]
LDQS
LDQS
UDQS
UDQS
refresh mode can be entered.
is entered. Data integrity will be maintained if
Bits
Bits
14
13
[12:0]
Type
w
Type
w
1)
1)
Description
Address Bus, Partial Array Self Refresh for 4 Banks
000
001
010
011
100
101
110
111
Description
Bank Adress[1]
1
Bank Adress[0]
1
Address Bus[12:0]
0
B
B
B
B
B
B
B
B
B
B
B
T
Case
PASR0 Full Array
PASR1 Half Array (BA[1:0]=00, 01)
PASR2 Quarter Array (BA[1:0]=00)
PASR3 Not defined
PASR4 3/4 array (BA[1:0]=01, 10, 11)
PASR5 Half array (BA[1:0]=10, 11)
PASR6 Quarter array (BA[1:0]=11)
PASR7 Not defined
BA1 Bank Address
BA0 Bank Address
A[12:0] Address bits
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10
≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
EMRS(1) Address Bit A10
X
X
X
0
X
0
t
REF
conditions are met and no Self Refresh command is issued
13
512-Mbit Double-Data-Rate-Two SDRAM
EMRS(1) Address Bit A11
X
X
3)
HYB18T512161B2F–20/25
Internet Data Sheet
ODT Truth Table
TABLE 10
TABLE 9
B
)