HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 8

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Abbreviation
SSTL
LV-CMOS
CMOS
OD
data strobe for DQ[7:0]
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
8
2. LDM is the data mask signal for DQ[7:0], UDM is the data
3.
mask signal for DQ[15:8]
V
connected to
and
DDL
Chip Configuration, PG-TFBGA-84 (top view)
V
and
SSQ
V
are isolated on the device.
512-Mbit Double-Data-Rate-Two SDRAM
SSDL
V
DD
are power and ground for the DLL.
on the device.
Abbreviations for Buffer Type
HYB18T512161B2F–20/25
V
DD
Internet Data Sheet
,
V
DDQ
FIGURE 1
TABLE 4
,
V
SSDL
,
V
V
DDL
SS
,
is