HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 28

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

12) The
13) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85 °C
14) 0 °C ≤
15) 85 °C <
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The maximum limit for the
18) WR must be programmed to fulfill the minimum requirement for the
19) Minimum
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
5.7.3
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
performance (bus turnaround) degrades accordingly.
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
the ODT resistance is fully on. Both are measure from
Both are measured from
t
HZ,
t
t
HZ
RPST
T
,
T
t
CASE
RPST
), or begins driving (
CASE
t
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
WTR
≤ 85 °C
and
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
LZ
ODT AC Electrical Characteristics
,
t
RPRE
t
XARDS
t
AOFD
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
t
t
DAL
LZ,
.
has to be satisfied.
parameter is not a device limit. The device operates with a greater value for this parameter, but system
t
= WR + (
RPRE
).
t
ODT AC Electrical Characteristics and Operating Conditions for all bins
HZ
t
RP
and
/
t
CK
t
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
transitions occur in the same access time windows as valid data transitions.These
t
AOND
t
.
XARD
Values
Min.
2
t
t
2.5
t
t
3
8
28
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
AC.MIN
AC.MIN
AC.MIN
AC.MIN
t
WR
timing parameter, where
+ 2 ns
+ 2 ns
512-Mbit Double-Data-Rate-Two SDRAM
Max.
2
t
2
2.5
t
2.5
—
—
AC.MAX
AC.MAX
t
CK +
WR
t
CK +
MIN
t
+ 0.7 ns
AC.MAX
+ 0.6 ns
t
[cycles] =
AC.MAX
HYB18T512161B2F–20/25
+ 1 ns
+ 1 ns
Internet Data Sheet
t
WR
(ns)/
TABLE 30
Unit
t
ns
ns
t
ns
ns
t
t
t
CK
CK
CK
CK
CK
(ns) rounded
Note
1)
2)
t
CK