MC908QL4 FREESCALE [Freescale Semiconductor, Inc], MC908QL4 Datasheet - Page 142

• Manufacturer Part Number: MC908QL4
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Slave LIN Interface Controller (SLIC) Module
SLCF — SLIC Interrupt Flag
14.8.4 SLIC Prescaler Register
SLIC prescaler register (SLCP) is used to configure the delay of the digital receive filter circuit, and hence
the width of noise pulse which is blocked by the filter. The SLIC clock is used to drive the digital receive
circuit. Variations on the input clock will affect filter performance proportionally, so if internal oscillators
are used, worst case oscillator frequencies must be accounted for when determining prescaler settings
to ensure that the frequency of the SLIC clock always remains between 2 MHz and 8 MHz.
RXFP[1:0] — Receive Filter Prescaler
The frequency of the SLIC clock must be between 2 MHz and 8 MHz, factoring in worst case possible
numbers due to untrimmed process variations, as well as temperature and voltage variations in oscillator
frequency. This will guarantee greater than 1.5% accuracy for all LIN messages from 1–20 kbps. The
faster this input clock is, the greater the resulting accuracy and the higher the possible bit rates at which
the SLIC can send and receive. In LIN systems, the bit rates will not exceed 20 kbps; however, the SLIC
module is capable of much higher speeds without any configuration changes, for cases such as
142
The SLCF interrupt flag indicates if a SLIC module interrupt is pending. If set, the SLCSV is then used
to determine what interrupt is pending. This flag is cleared by writing a 1 to the bit. If additional interrupt
sources are pending, the bit will be automatically set to 1 again by the SLIC.
These bits configure the effective filter width for the digital receive filter circuit. The RXFP bits control
the maximum number of SLIC clock counts required for the filter to change state, which determines
the total maximum filter delay. Any pulse which is smaller than the maximum filter delay value will be
rejected by the filter and ignored as noise. For this reason, the user must choose the prescaler value
appropriately to ensure that all valid message traffic is able to pass the filter for the desired bit rate. For
more details about setting up the digital receive filter, please refer to
1 = SLIC interrupt pending
0 = No SLIC interrupt pending
Reset:
Read:
Write:
RXFP[1:0]
$00
$01
$10
$11
RXFP1
Bit 7
1
Table 14-1. Digital Receive Filter Clock Prescaler
Figure 14-7. SLIC Prescale Register (SLCP)
= Unimplemented
RXFP0
Digital RX Filter
Clock Prescaler
6
0
(Divide by)
3 (default)
MC68HC908QL4 Data Sheet, Rev. 7
1
2
4
5
0
0
16
24
32
4
0
0
2
8
Maximum Filter Delay (in μs)
3.2
10
15
20
5
3
0
0
SLIC Clock (in MHz)
12
16
4
4
8
2
0
0
10.67
2.67
5.33
14.9.17 Digital Receive
6
8
1
0
0
6.4
2.5
7.5
10
5
Freescale Semiconductor
Bit 0
0
0
8
2
4
6
8
Filter.