MC908QL4 FREESCALE [Freescale Semiconductor, Inc], MC908QL4 Datasheet - Page 144

• Manufacturer Part Number: MC908QL4
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Slave LIN Interface Controller (SLIC) Module
BT — Bit Time Value
14.8.6 SLIC State Vector Register
SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly
related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly
enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state
machine in software.
READ: any time
WRITE: ignored
I[3:0] — Interrupt State Vector (Bits 5–2)
14.8.6.1 LIN Mode Operation
Table 14-2
operation (BTM = 0).
144
BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0). For details of
the use of the SLCBT registers in LIN mode for trimming of the internal oscillator, refer to
Oscillator Trimming with
BT sets the number of SLIC clocks that equals one bit time in byte transfer mode (BTM = 1). For details
of the use of the SLCBT registers in BTM mode, refer to
These bits indicate the source of the interrupt request that is currently pending.
shows the possible values for the possible sources for a SLIC interrupt while in LIN mode
Reset:
Read:
Write:
Do not write to unimplemented bits as unexpected operation may occur.
SLCSV
$0C
$00
$04
$08
$10
$14
$18
Bit 7
0
0
Figure 14-10. SLIC State Vector Register (SLCSV)
Table 14-2. Interrupt Sources Summary (BTM = 0)
I3
0
0
0
0
0
0
0
SLIC.
= Unimplemented
I2
0
0
0
0
1
1
1
6
0
0
I1
0
0
1
1
0
0
1
MC68HC908QL4 Data Sheet, Rev. 7
I0
0
1
0
1
0
1
0
I3
5
0
TX Message Buffer Empty
TX Message Buffer Empty
NOTE
RX Message Buffer Full
Checksum Transmitted
I2
4
0
No Interrupts Pending
RX Data Buffer Full
Interrupt Source
No-Bus-Activity
Checksum OK
No Errors
Bit-Error
I1
3
0
14.9.15 Byte Transfer Mode
I0
2
0
1
0
0
0 (Lowest)
Priority
1
2
3
4
5
6
Freescale Semiconductor
Bit 0
0
0
Operation.
14.9.16