MC908QL4 FREESCALE [Freescale Semiconductor, Inc], MC908QL4 Datasheet - Page 53

• Manufacturer Part Number: MC908QL4
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

ADCH[4:0] — Channel Select Bits
Freescale Semiconductor
(with ACLKEN low), continuous conversions will cease and can be restarted only with a write to
ADCSC. Any write to ADCSC with ADCO set and the ADCH bits not all 1s will abort the current
conversion and begin continuous conversions.
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADCSC
is written (assuming the ADCH[4:0] bits do not decode all 1s).
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
1 = Continuous conversion following a write to ADCSC
0 = One conversion following a write to ADCSC
1. If any unused or reserved channels are selected, the resulting conversion will be unknown.
2. Requires LVI to be powered (LVIPWRD = 0, in CONFIG1)
ADCH4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
ADCH3
Table
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Continuing through
3-2. The successive approximation converter subsystem is turned off
Table 3-2. Input Channel Select
MC68HC908QL4 Data Sheet, Rev. 7
ADCH2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
ADCH1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BANDGAP REF
Low-power state
Input Select
Reserved
Reserved
Unused
Unused
Unused
V
V
AD0
AD1
AD2
AD3
AD4
AD5
REFH
REFL
(1)
(2)
Registers
53