M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 106

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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10. Watchdog Timer
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Figure 10.1 Watchdog Timer Block Diagram
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The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is
recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is
decremented by the CPU clock that the prescaler divides. The PM12 bit in the PM1 register determines whether
to generate a watchdog timer interrupt request or reset the watchdog timer when the watchdog timer underflows.
The PM12 bit can only be set to “1” (reset). Once the PM12 bit is set to “1”, it cannot be changed to “0” (watchdog
timer interrupt) by program. Refer to “5.3 Watchdog Timer Reset” for watchdog timer reset.
When the main clock, on-chip oscillator clock, or PLl clock runs as CPU clock, the WDC7 bit in the WDC register
determines whether the prescaler divides the clock by 16 or 128. When the sub clock runs as CPU clock, the
prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as
follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
For example, when CPU clock is set to 16 MHz and the divide-by-N value for the prescale ris set to 16, the
watchdog timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that
the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start
counting by writing to the WDTS register.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held
value when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related
registers.
0
C
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period =
2
9
0 .
2 /
Internal reset signal
(low active)
B
CPU clock
0
0
8
0
4
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7
a
Write to WDTS register
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2
3
p
0
, 1
0
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2
0
1
0
6
7
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2 /
, 8
On-chip oscillator clock
page 86
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Prescaler
1
1/128
6
1/16
1/2
C
f o
2 /
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Prescaler dividing (2) X Watchdog timer count (32768)
8
3
CM07 = 0
WDC7 = 1
CM07 = 1
) B
CM07 = 0
WDC7 = 0
8
5
PM22 = 0
PM22 = 1
CPU clock
CPU clock
Watchdog timer
Set to 7FFF
16
PM12 = 0
PM12 = 1
10. Watchdog Timer
Reset
Watchdog timer
interrupt request