M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 191

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M
R
R
1
e
E
Figure 14.6 U0C0 to U2C0 and UCON Registers
. v
6
J
0
C
2
9
2 /
0 .
B
8
0
0
0
G
NOTES:
4
J
7
a
o r
1. Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
2. Effective when the SMD2 to SMD0 bits in the UMR register to "001
3. CTS
4. SDA2 and SCL2 are effective when i = 2.
5. When the SMD2 to SMD0 bits in UiMR regiser are set to “000
6. When the U1MAP bit in PACR register is “1” (P7
7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.
0 -
UARTi Transmit/receive Control Rregister 0 (i=0 to 2)
. n
b7
u
transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "101
they are set to"100
UCON register is set to “0” (CTS
SCL2 pins are N-channel open-drain output).
2
UART Transmit/receive Control Register 2
b7
p
3
NOTES:
b6
0
, 1
0
(
1
b6
/RTS
1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to “0” (internal clock).
2. When the U1MAP bit in PACR register is set to “1” (P7
M
b5
2
1
0
b5
b4
0
6
1
7
can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK
C
b4
b3
2 /
b3
b2
, 8
page 171
2
" (UART mode transfer data 7 bits long) or "110
b1
b2
M
b0
b1
1
6
UFORM Transfer format select bit
Symbol
CKPOL
b0
TXEPT
C
CRS
CLK0
CLK1
CRD
NCH
Bit
2 /
f o
Bit Symbol
0
CLKMD0
CLKMD1
Symbol
U0C0 to U2C0
U0RRM
U1RRM
8
/RTS
U0IRS
U1IRS
RCSP
3
) B
(b7)
8
(2)
BRG count source
select bit
CTS/RTS function
select bit
Transmit register empty
flag
CTS/RTS disable bit
Data output select bit
CLK polarity select bit
Symbol
UCON
5
0
not separated).
Bit Name
UART0 transmit interrupt
cause select bit
UART1 transmit interrupt
cause select bit
UART0 continuous
receive mode enable bit
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 CLK/CLKS
select bit 1
Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set to “0”.
When read, the content is indeterminate
(3)
(7)
3
to P7
Address
03A4
Bit Name
0
), CTS/RTS pin in UART1 is assigned to P7
16
(1)
Address
03B0
, 03AC
(5)
2
” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and
16
0 0 : f
0 1 : f
1 0 : f
1 1 : Do not set
Effective when CRD is set to "0"
0 : CTS function is selected
1 : RTS function is selected
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : TxD2/SDA2 and SCLi pins are CMOS output
1 : TxD2/SDA2 and SCLi pins are N-channel open-drain output
0 : LSB first
1 : MSB first
b1 b0
0 : Transmit data is output at falling edge of transfer clock
1 : Transmit data is output at rising edge of transfer clock
3
16
2
to P7
(P6
(transmission completed)
and receive data is input at rising edge
and receive data is input at falling edge
"(clock synchronous serial I/O mode) or "010
2
, 037C
" ( UART mode transfer data 9 bits long).
1SIO
8SIO
32SIO
0
, P6
0
), CTS
or f
is selected
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enable
0: Continuous receive mode disabled
1: Continuous receive mode enabled
Effective when CLKMD1 bit is set to “1”
0: Clock output from CLK1
1: Clock output from CLKS1
0: Output from CLK1 only
1: Transfer clock output from multiple
0: CTS/RTS shared pin
1: CTS/RTS separated (CTS
16
is selected
4
pins function selected
from the P6
and P7
2SIO
0
After Reset
X0000000
After Reset
00001000
is supplied from the P7
is selected
3
can be used as I/O ports)
4
2
pin)
1
2
Function
(1)
output) and the RCSP bit in the
Function
(2)
2
" (I
2
C bus mode) and "0" when
0
.
0
0
supplied
pin.
(6)
2
" (UART mode
RW
RW
RW
RW
RW
RW
RW
RW
(4)
RW
RW
RW
RW
RW
RW
RO
RW
14. Serial I/O
RW