M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 295

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M30280F6HP

Manufacturer Part Number
M30280F6HP
Description
16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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R
R
M
e
E
1
. v
NOTE:
J
6
Table 16.8 Start/Stop generation timing table
Table 16.9 S10 Register Settings and Functions
Figure 16.16 Start condition generation timing diagram
Figure 16.17 Stop condition generation timing diagram
0
M
As mentioned above, when the MST and TRX bits are set to "1", START condition or STOP condition mode
is entered by writing "1" or "0" to the BB flag in the S10 register and writing "0" to the PIN bit and 4 low-order
bits in the S10 register at the same time. Then SDA
and SDA
START/STOP conditions are generated. In order to set the MST and TRX bits to "1" without generating the
START/STOP conditions, write "1" to the 4 low-order bits simultaneously. Table 16.9 lists functions along
with the S10 register settings.
C
0
2
9
S
H
S
1
1
1. Actual time at the time of V
1 /
0 .
2 /
B
e
T
o
0
0
u t
8
d l
0
p
4
G
J
T
i t
7
a
i t
0
o r
R
m
0 -
. n
1
1
m
1 /
MM
X
u
e
2
e
3
p
0
, 1
0
is set to low-level ("L") in the STOP condition standby mode. When the S00 register is set, the
(
M
B
2
0
1
-
0
S
B
1
0
1
6
7
G
0
C
S
I
write signal
2
e
R
a t
2 /
I
write signal
C0 data shift register
P
n
2
page 275
e
0
0
0
t r
, 8
C0 data shift register
r e
N I
g
S /
t s i
t a
M
o t
o i
r e
1
p
A
n
6
0
0
1
1
0
0
S
1
L
C
C
S
e
o
f o
2 /
S
S
e
t t
n
CL
DA
e l
S
S
IIC
n i
8
d
3
A
CL
DA
t c
g
) B
t i
8
A
0
0
1
s
= 4MHz, The contents in () denote cycle numbers.
o i
5
S
B
n
t i
A
S
0
0
1
0
Setup
L
time
S
Setup
R
0
0
time
1
1
1
a t
B
5
5
3
3
n
0 .
0 .
0 .
0 .
d
MM
a
S
S
S
I
t
t
2
a r
a r
d r
C
e
e
e
s
s
s
s
t t
n
t t
n
t t
is left open in the START condition standby mode
2 (
5 (
2 (
5 (
s
C
n i
s
n i
s
n i
a t
m
m
o l
0
2
0
2
g
g
g
Hold
time
t i
t i
u t
k c
Hold
c
c
time
c
c
u
u
u
c y
c y
c y
c y
m
m
p
p
p
s
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h t
e
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e l
e l
e l
d
d
a
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c
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t s
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t a
g i
o i
t i
t c
2
6
2
6
o i
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h
n
o i
5 .
5 .
5 .
5 .
s -
n
n
s
n
p
a t
m
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s
s
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1 (
2 (
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b
0
6
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6
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2
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c
c
c
c
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C bus INTERFACE
f e
n i
c y
c y
c y
c y
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m
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m
M
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a
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5 .

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