LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 158

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

March 22, 2006
Reset
Reset
Type
Type
GPTM TimerA (GPTMTAR)
Offset 0x048
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
31:16
RO
RO
1/0
31
15
1
15:0
Bit
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge
Count mode. When in this mode, this register contains the time at which the last edge event took
place.
RO
RO
1/0
30
14
1
Name
TARH
TARL
RO
1/0
RO
29
13
1
RO
1/0
RO
28
12
1
Type
RO
RO
RO
1/0
RO
27
11
1
RO
RO
1/0
26
10
1
0xFFFF
0xFFFF
0x0000
(32-bit
mode)
(16-bit
mode)
Reset
RO
RO
1/0
25
9
1
Preliminary
Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
GPTM TimerA Register Low
A read returns the current value of the TimerA Count Register,
except in Input Edge Count mode, when it returns the
timestamp from the last edge event.
RO
1/0
RO
24
8
1
TARH
TARL
RO
1/0
RO
23
7
1
RO
RO
1/0
22
6
1
RO
RO
1/0
21
5
1
RO
1/0
RO
20
4
1
RO
1/0
RO
19
3
1
LM3S101 Data Sheet
RO
RO
1/0
18
2
1
RO
RO
1/0
17
1
1
RO
1/0
RO
16
0
1
158