LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 69
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 69 of 284
- Download datasheet (3Mb)
System Control
69
Reset
Reset
Type
Type
Bit/Field
31:6
Reset Cause (RESC)
Offset 0x05C
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 16: Reset Cause (RESC), offset 0x05C
This field specifies the cause of the reset event to software. The reset value is determined by the
cause of the reset. When an external reset is the cause (EXT is set), all other reset bits are
cleared. However, if the reset is due to any other cause, the remaining bits are sticky, allowing
software to see all causes.
RO
RO
30
14
0
0
reserved
Name
WDT
BOR
POR
LDO
EXT
SW
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
-
-
-
-
-
-
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
When set to 1, LDO power OK lost is the cause of the reset
event.
When set to 1, a software reset is the cause of the reset
event.
When set to 1, a watchdog reset is the cause of the reset
event.
When set to 1, a brown-out reset is the cause of the reset
event.
When set to 1, a power-on reset is the cause of the reset
event.
When set to 1, an external reset (RST assertion) is the
cause of the reset event.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
LDO
RO
R/W
21
0
5
-
SW
RO
R/W
20
0
4
-
WDT
R/W
RO
19
0
3
-
BOR
RO
R/W
18
0
2
-
March 22, 2006
POR
R/W
RO
17
0
1
-
EXT
RO
R/W
16
0
0
-
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